In the manufacture of semiconductor devices, patterned substrates are inspected for defects so that the production of acceptable devices can be achieved. Inspection of a patterned substrate can be carried out through various technologies, one of which is charged particle beam inspection. A common example of charged particle beam inspection is electron beam (EB) inspection.
EB inspection is performed by scanning an electron beam over surface patterns of devices formed on a substrate, and collecting the secondary electrons emanated from the surface patterns of scanned devices as inspection signals. The signals are processed and represented in grey levels to produce images of surface patterns of the scanned devices.
The patterned surface contains pattern features which either form the electrical devices or direct/indirect electrical connect to the buried devices. The obtained image shown in grey level contrast represents the difference in electrical charging voltages associated with the devices, connections, as well as the materials. The image is thus also known as a voltage contrast (VC) image. Abnormal grey levels, or abnormal VCs, are detected to identify defective devices or connections. For example, if a bright grey level shows up where a darker grey level should have been observed, it is deemed there exists a bright voltage contrast (BVC) defect. On the other hand, if a dark grey level shows up where a brighter grey level should have been observed, it is deemed there exists a dark voltage contrast (DVC) defect.
When the electron beam is scanned over the surface pattern of a device, charging may be induced and accumulate on the device. The resulting charging can be negative or positive, depending on the electron beam conditions (landing energy, beam current, etc.) used, as well as surface pattern materials in exposure to electron beam scanning. In this specification, for a given surface layer of a device, an electron beam condition leading to accumulation of positive charging on the scanned device will be referred to as “positive imaging mode.” On the other hand, an electron beam condition leading to accumulation of negative charging on the scanned device will be referred to as “negative imaging mode.”
The positive imaging mode or negative imaging mode may lead to different voltage contrast images for a given surface layer of devices. For example, for the positive imaging mode, an open circuit defect may appear relatively dark in the image due to excessive positive charging accumulated if a normal feature is expected to be well grounded, and display a DVC. On the other hand, a short circuit defect may appear relatively bright due to the formed release path of charging if a normal feature is expected to be floated, and display a BVC in the image.
When a semiconductor device is being scanned in a particular imaging mode, its electrical characteristics give rise to a default VC for this device. For instance, metal contact plugs coupled to the same PN junction device may display different VCs in the positive and negative imaging mode, respectively. Taking the positive imaging mode as an example, PN junctions in a normal NMOS device, such as an n-doped region or a plug connected thereto, are typically reverse biased when being scanned in the positive imaging mode, whereas PN junctions in a normal PMOS device, such as a p-doped region or a plug connected thereto, are typically forward biased when being scanned in the positive imaging mode. The biasing condition of these devices affects their VC behaviors, as will be illustrated below.
Referring to the drawings, FIG. 1 is a schematic illustration of MOSFET devices after the process step of metal CMP (Chemical Mechanical Planarization) in the positive imaging mode. FIG. 1A is a schematic illustration of a PMOS transistor being imaged in the positive imaging mode in accordance with the conventional art, and FIG. 1B is a schematic illustration of an NMOS transistor being imaged in the positive imaging mode in accordance with the conventional art.
As shown in FIG. 1A, PMOS transistor 100A comprises a gate plug 101A, a normal P+/N-well plug 102A, an open P+/N-well plug 103A, and a shorted P+/N-well plug 104A. Image 110A illustrates VC behaviors of the respective above components. As the surface is positively charged, normal P+/N-well junction associated to plug 102A is forward biased, thus is in the “ON” state whereby excessive positive charges can be released to N-well via the junction. A normal P+/N-well plug 102A is therefore, to some extent, equivalent to being shorted/leaking to substrate, and appears bright in the voltage contrast image 110A. P+/N-well plug 104A can be shorted to the substrate or gate plug (for example, short/leakage to the substrate is illustrated in the figure as a black strip 107A connecting plug 104A and N-well). Charges on plug 104A can thus be easily released to N-well or substrate regardless of the ON/OFF state of the P+/N-well junction associated to plug 104A. As a result, plug 104A appears brighter in the VC image 110A. Another typical defect is open P+/N-well plug 103A, i.e. the plug does not contact to the buried device as expected. As a result, positive charges on the surface of P+/N-well plug 103A accumulate to a significant level, and deliver a voltage contrast much darker than the normal plugs 102A. The gate plug 101A is equivalent to an open circuit as it is electrically isolated from the substrate (N-well) by a gate dielectric layer 105A, so it appears similar to the open P+/N-well plug 103A. As one can perceive from the image 110A, for inspection of PMOS plugs at a given positive mode imaging condition, it will be easy to identify the defective open P+/N-well plugs 103A from normal P+/N-well plugs 102A with high sensitivity, but difficult or insensitive to identify the P+/N-well short/leakage defects 104A from normal P+/N-well plugs 102A.
Similar inspection of the NMOS transistor is illustrated in FIG. 1B. As shown, NMOS transistor 100B comprises a gate electrode 101B, a normal N+/P-well plug 102B, an open N+/P-well plug 103B, and a shorted N+/P-well plug 104B. Image 110B illustrates the VC behaviors of respective above components. As the surface is positively charged, the N+/P-well junction associated to plug 102B is reverse biased. Therefore, the junction is in the “OFF” state and to some extent equivalent to being an open circuit. As a result, positive charging accumulates on N+/P-well plug 102B, making it appear dark in image 110B. Though the open plug 103B differs from the normal plug 102B in that it is a real open-circuit to the associated buried N+/P-well junction, no significant difference in image contrast is observed between plugs 102B and 103B as they hold the positive charging to a similar level. In real cases, minor junction leakage may exit on the reverse biased N+/P-well junction, thus a normal N+/P-well plug 102B may appear slightly brighter than an open plug 103B as shown in image 110B. Another defect type is junction short or leakage in which the N+/P-well plug 104B may be either leaking a current or directly shorted to the substrate (illustrated in the figure as a black strip 107B connecting plug 104B and P-well). A plug of this defect type releases charges effectively even with its associated junction reverse biased to the OFF state. As a result, shorted plug 104B appears much brighter in image contrast. Gate plug 101B is equivalent to an open circuit as it is electrically isolated from the substrate (P-well) by a gate dielectric layer 105B. Therefore, it appears similar to the open N+/P-well plug 103B in the VC image 110B (darker VC). Hence, it can be perceived from FIG. 1B that for inspection of NMOS plugs at a given positive mode imaging condition, it is difficult or insensitive to identify the defective open N+/P-well plugs 103B from the normal N+/P-well plugs 102B, but it is sensitive to identify the P+/N-well short or leakage defects 104B from normal N+/P-well plugs 102B.
Therefore, a conclusion can be drawn that the positive mode EBI has high sensitivity to capture P+/N-well plug open defects, but suffers low sensitivity in detecting N+/P-well plug open. Different approaches have been proposed to improve the situation, for example, by applying strong extraction field to reversely breakdown the N+/P-well junction, or by charging the sample surface negatively to forward bias the N+/P-well junction (the negative mode scanning). These techniques either suffer high risk of wafer arcing damage as extremely high electrical field is created in the vicinity of wafer, or need at least two separate inspections to detect both the P+/N-well plug open and the N+/P-well plug open, which is time costly.
Another approach to boost the detection sensitivity of, for example, the open N+/P-well plug at the positive imaging mode was proposed by Larry (U.S. Pat. No. 4,902,967). The proposed method uses an optical beam which has energy higher than the band gap to illuminate the device under inspection. Photo-current will be induced while the surface of the device is being scanned, which either induces photocurrent across the N+/P-well junction, or stimulates leakage current across the thin gate oxide. Ground or substrate electrons are able to come up and neutralize the positive charging accumulated on the scanned surface of the device, and the N+/P-well junctions in the scanned device become, to some extent, leaking or shorted regardless of its actual biasing condition (forward or reverse biased) in the normal positive imaging mode. This helps to drain off the accumulated positive charges on the scanned device, especially the reverse biased N+/P-well junctions as illustrated in FIG. 1B.
Referring to FIG. 1C, an NMOS transistor 100C is illustrated being imaged in the positive imaging mode with optical beam illumination in accordance with the conventional art. The NMOS transistor 100C comprises a gate electrode 101C, a normal N+/P-well plug 102C, an open N+/P-well plug 103C, and a shorted N+/P-well plug 104C. Image 110C illustrates the VC behaviors of respective above components. As shown, optical beam illumination stimulates photo-currents. In the presence of the photo-currents, ground or substrate electrons are able to come up and neutralize the positive charging accumulated on the scanned device surface. This helps to drain off the charging accumulated on normal N+/P-well plug 102C. As a result, plug 102C turns bright in image 110C, and thus the contrast between a normal N+/P-well plug 102C and an open N+/P-well plug 103C which appears dark is greatly enhanced whereby detection sensitivity of open N+/P-well plug 103C is improved. It is noted that gate plug 101C also turns relatively brighter as compared to the gate plug 101B of FIG. 1B (inspection without optical illumination). This is due to the stimulated leakage in gate oxide 105C. This phenomenon can be used to separate the normal gate plug and the open gate contact which does not physically land on gate electrode.
One disadvantage of the above approach is that the optical beam will stimulate the normal N+/P-well plug 102C to leak, thus the N+/P-well leakage or short defects such as plug 104C may become difficult to detect. As a result, at least two inspection actions are still needed to accomplish the detection of both the of-interest open and short/leakage defects.
Referring to FIG. 2A, not admitted art, a positive imaging mode VC image is captured, without optical illumination, of a sample containing both NMOS and PMOS transistors. The sample device can be, for example, an SRAM device. Herein, defect 200 A is a P+/N-well open defect displaying a DVC (visually distinguishable), defect 200B is an N+/P-well leakage/short defect displaying a BVC (visually distinguishable), defect 200C is an open N+/P-well plug defect displaying a DVC (less distinguishable). Defect 200D is an open gate contact displaying a DVC (less distinguishable); as shown it is immersed in the normal gate plugs as there are no substantial electrical differences between them. Furthermore, defect 200E is a gate short/leakage defect displaying a BVC (visually distinguishable). No P+/N-well leakage or short defect (BVC) is present in FIG. 2A. In the schematic of FIG. 2B, not admitted art, a positive imaging mode VC image is captured, with optical beam illumination, of the sample device of FIG. 2A. As with the FIG. 2A schematic, the image is captured in positive imaging mode. It can be seen from FIG. 2B that with optical beam illumination all normal N+/P-well plugs turn bright. As a result, the N+/P-well leakage/short defect 200B becomes hidden (less distinguishable) in the normal bright plugs, and the open N+/P-well plug defect 200C stands out (visually distinguishable) as a high contrast dark plug. It is noted that the P+/N-well plug open defect 200A is almost unaffected by the optical beam illumination (visually distinguishable). Also, the optical beam illumination, by stimulating certain level of leakage through the thin gate oxide, turns the gate plug relatively bright. The gate plug defect 200E thus becomes less distinguishable. The open gate plug defect 200D, however, is not affected by this induced gate oxide leakage, thus standing out (visually distinguishable) as a darker plug.
In general processes of semiconductor device manufacture, it is common to see both NMOS and PMOS plugs in a layer from the surface. FIGS. 2A and 2B illustrate complementary images, or complementary imaging approaches, for detecting different types of defects present on a single sample. These complementary approaches may be implemented in the negative imaging mode and applied to other types of devices as well. Since these complementary approaches only require changes in optical beam illumination condition (on/off), there will be a great benefit to combine the above two imaging steps (one with optical beam illumination, the other without) into one imaging sequence for improved throughput without sacrificing the detection sensitivity to different types of defects.